Conventional buffer circuits include a single input translator, i.e. level shifter, that receives an input signal with TTL logic levels (0 V is low, 3.0 V is high) and that translates that signal to CMOS logic levels (0 V is low, 5.0 V is high). In both cases the nominal transition point is 1.5 V. This translated signal is then reinverted through a CMOS inverter, since the translator usually has an inverting as well as translating function, and then goes through a set of logic gates. The logic gates include a disable input so that a high impedance state can be asserted if desired. The set of logic gates then drives pull-up and pull-down output transistors connected to an output line. One problem with such buffer circuits is that of noise generation. While the input signal has a relatively slow ramp rate (3 V/2.5 ns), by the time the signal has made successive transitions in the translator, inverter and logic gates, the ramp rate is approximately 8 times higher (5 V/0.5 ns). This causes the output transistors to open and close quickly, which produces ground bounce or overshoot of the output signal due to the inductance between the integrated circuit chip's internal ground and power supply and external ground and power supply. The buffer circuit also has a relatively slow throughput time due to the many layers of logic between the input and output of the circuit. An ideal buffer would be relatively fast and yet would linearly ramp its output current to a maximum to reduce ground bounce or overshoot and then linearly ramp down its output current to source small DC current sufficient to maintain the final voltage on the output line. It would also reject input noise spikes instead of transmitting them to the output.
In U.S. Pat. No. 5,381,059, Douglas describes a tristate buffer circuit with parallel pairs of pull-up and pull-down transistors that are driven by separate control signals. A feedback circuit coupled between the output node and the pull-up transistors prevents leakage current from flowing in the buffer. Like conventional circuits, there is considerable logic between the data input terminal and the transistors in the output stage.
In U.S. Pat. No. 5,355,029, Houghton et al. describe a circuit with parallel drivers, each with their own predriver stage. Like conventional buffers, the predriver stages consist of transistors forming AND and NOR gates connected to the output of a single input transistor.
In U.S. Pat. No. 4,806,794, Walters, Jr. describes a buffer circuit with an output stage having dynamic pull-up and pull-down circuit elements that drive the output transistors and a keeper circuit element. The keeper maintains the output node at the high or low logic level after it has completed a low-to-high or high-to-low transition. In this case, "after" is defined with respect to a delay generated by the circuitry. Since the delay is a function of the load that the current is driving, proper operation depends to some extent on the load being known. For example, a buffer circuit of this type with a 4.2 nsec propagation time when driving a 50 pF load would have a 10.2 nsec propagation time when driving a 250 pF load. It is desirable in buffer circuits to have the propagation time generally independent of the load, since the load is usually not known in advance.
An object of the present invention is to provide a buffer circuit which is faster, rejects input noise spikes and does not generate noise at the output, and which has low power dissipation.